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PLL650-02
Low EMI Network LAN Clock
FEATURES
* * * * * * * * * *
*
PIN CONFIGURATION
VDD XIN XOUT/50MHz_OE*^ GND VDD 50MHz/FS0*^ GND 50MHz/FS1*^ 50MHz/FS2*T FS3T 50MHz/SS0*T VDD 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD VDD 25MHz/100MHz GND SDRAMx2 GND SDRAMx2 VDD VDD 25MHz/125MHz GND 25MHz/125MHz
Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 4 outputs at 50MHz, 2 outputs selectable at 25MHz or 125MHz, 1 output selectable at 25MHz or 100MHz. 2 SDRAM selectable frequencies of 66.6, 75, 83.3, 100MHz (Double Drive Strength). All non SDRAM outputs can be disabled (tri-state) Spread spectrum technology selectable for EMI reduction from 0.5%, 0.75% for SDRAM and 100MHz output. Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 24-Pin 150mil SSOP.
Note: SDRAMx2: Double Drive strength. T: Tri-Level input ^: Internal pull-up resistor. *: Bi-directional pin (input value is latched upon power-up).
PLL650-02
DESCRIPTIONS
The PLL 650-02 is a low cost, low jitter, and high performance clock synthesizer. With PhaseLink's proprietary analog Phase Locked Loop techniques, the chip accepts 25 MHz crystal, and produces multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs, with double drive strength for its SDRAM outputs.
FREQUENCY TABLE
FS1 0 0 1 1 FS0 0 1 0 1 SDRAM 100MHzSST 75MHz SST 83.3MHzSST 66.6MHzSST FS3 0 M 1 Pin 13, 15 Disable 125MHz 25MHz FS2 0 M 1 Pin 22 25MHz Disable 100MHzSST
FS(2:3): Tri-level inputs. SST: SST modulation applied (see selection table)
BLOCK DIAGRAM
4 XIN XOUT
XTAL OSC
50MHz (can be disabled) 25MHz/125MHz (can be disabled)
2
Control Logic
FS (0:3)
2
SDRAM (66.6, 75, 83.3, 100MHz)
1
25MHz/100MHz (can be disabled)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/02/01 Page 1
PLL650-02
Low EMI Network LAN Clock
PIN DESCRIPTIONS
Name
XIN XOUT/50MHz_OE 50MHz/FS(0:2) 50MHz/SS0 FS3 25MHz/125MHz SDRAMx2 25MHz/100MHz VDD GND
Number
2 3 6,8,9,11 10 13,15 18,20 22 1,5,12, 16,17,23,24 4,7,14,19,21
Type
I B B I O O O P P
Description
25MHz fundamental crystal input (20pF CL parallel resonant). CL have been integrated into the chip. No external CL capacitor is required. Crystal connection pin. At power-up, this pin latches 50MHz_OE (output enable selector for all 50MHz outputs. Disabled when 50MHz_OE is logical zero. Has 120k internal pull up resistor. Bi-directional pins. 50MHz outputs. These pins latch FS(0:2) and SS0 at power-up. 60k internal pull up resistors on pins 6 and 8. Tri-level input pin. FS3 input put. 25MHz (reference) or 125MHz outputs. Can be disabled with FS3 = 1. SDRAM outputs with double drive strength determined by FS(0:1) value. 25MHz (reference) or 100MHz output. Can be disabled with FS2 = M. 3.3V power supply. Ground.
SPREAD SPECTRUM SELECTION TABLE
SS0
0 M 1
SST modulation
0.75% center OFF 0.5% center
FUNCTIONAL DESCRIPTION Selectable spread spectrum and output frequencies
The PLL650-02 provides selectable spread spectrum modulation and selectable output frequencies. Selection is made by connecting specific pins to a logical "zero" or "one", or by leaving them not connected (tri-level inputs or internal pull-up) according to the frequency and spread spectrum selection tables shown on pages 1 and 2 respectively. In order to reduce pin usage, the PLL650-02 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 (Connect to GND), 1 (Connect to VDD), M (Do not connect). Thus, unlike the two-level selection pins, the tri-level input pins are in the "M" (mid) state when not connected. In order to connect a tri-level pin to a logical "zero", the pin must be connected to GND. Likewise, in order to connect to a logical "one" the pin must be connected to VDD. Pin 3 (XOUT/50MHz_OE) is a bi-directional pin used to disable the 50MHz output pins. Pin 6 (FS0) and pin 8 (FS1) are bidirectional pins used to select the SDRAM output frequency upon power-up. Pin 9 (FS2) and pin 11 (FS3) are tri-level bidirectional pins used to select the output frequency of pins 13, 15 and 22, as shown in the frequency table on page 1. After the input signals have been latched, pins 6, 8, 9, and 11 serve as 50 MHz frequency outputs.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/02/01 Page 2
PLL650-02
Connecting a bi-directional pin
Low EMI Network LAN Clock
A bi-directional pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up resistor. Note: when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor may not be sufficient to pull the input up to a logical "one", and an external pull-up resistor may be required. For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical "zero"). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application Diagram). Note: when the output is used to drive a load presenting an small resistance between the output pin and VDD, this resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical "zero". This is particularly true when driving 74FXX TTL components.
APPLICATION DIAGRAM
Internal to chip VDD
External Circuitry
Rup Power Up Reset
R RB
Output
EN
Bi-directional pin
Clock Load
Latched Input
Latch
RUP/4
Jumper options
NOTE: Rup=120k for 50MHz/OE (Pin3); Rup=60k
for FS(0:1) . R starts from 1 to 0 while RB starts from 0 to 1.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/02/01 Page 3
PLL650-02
Low EMI Network LAN Clock
Electrical Specifications
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature Storage Temperature Ambient Operating Temperature TS -65 0
SYMBOL
V CC VI VO
MIN.
MAX.
7 V CC +0.5 V CC +0.5 260 150 70
UNITS
V V V C C C
-0.5 -0.5 -0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. AC Specification PARAMETERS
Input Frequency Output Rise Time Output Fall Time Duty Cycle* Max. Absolute Jitter Max. Jitter, cycle to cycle 0.8V to 2.0V with no load 2.0V to 0.8V with no load At VDD/2 Short term 45 50 150 80
CONDITIONS
MIN.
10
TYP.
25
MAX.
27 1.5 1.5 55
UNITS
MHz ns ns % ps ps
* : in case SDRAM output is selected to be 83.3MHz, the duty cycle of output pin 22 will be 40%-60% if its output frequency is selected to be 100MHz (FS2=1). In all other situations, pin 22 will also have a 50%-50% typical duty cycle.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/02/01 Page 4
PLL650-02
Low EMI Network LAN Clock
3. DC Specification PARAMETERS
Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage At CMOS Level Operating Supply Current Short-circuit Current Nominal output current* Nominal output current* Internal pull-up resistor Internal pull-up resistor
SYMBOL
VDD VIH VIL VIH VIL VIH VIL VOH VOL VOH IDD IS Iout Iout Rup Rup
CONDITIONS
MIN.
3.13
TYP.
VDD/2 VDD/2
MAX.
3.47 VDD/2 - 1 0.5
UNITS
V V V V V V V V V V
For all Tri-level input For all Tri-level input For all normal input For all normal input IOH = -25mA IOL = 25mA IOH = -8mA No Load CMOS output level TTL output level Pins 6,8 Pin 3
VDD-0.5 2 0.8 2.4 0.4 VDD-0.4 35 100 35 20 40 25 60 120
mA mA mA mA k k
*: SDRAM output strengths are doubled (i.e. min. CMOS level is 70mA, typ. CMOS level is 80mA)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/02/01 Page 5

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